1. Field of the Invention
The present invention relates to a method and apparatus for localizing point defects causing column leakage currents (IL) between drains and sources, by means of source diffusion addressing in a conventional non-volatile memory device.
2. Discussion of the Related Art
In non-volatile memories, sometimes there are defects causing column (bit line) leakage currents, independent of the voltage applied to the gate electrode (word line). Such leakage currents can be caused by one or more defective contacts or by a conductive path between the drain electrode and the source electrode, e.g. in the silicon substrate, of one or more cells connected to the bit line wherein the above-mentioned leakage currents appear, as well as by contact-polysilicon or metal levels short-circuits, which depend on the particular device.
The use of failure analysis, usually long and delicate, is made extremely hard due to the practical impossibility of localizing the cell in which the leakage defect is located, because all the drain electrodes of the cells connected to the bit line at issue have the same potential value and also all the source electrodes of the matrix cells are short-circuited to each other by means of metal lines.
FIG. 1 schematically shows a top view of a matrix portion of memory cells according to the prior art, arranged in couples of rows (word lines 1) and in columns (bit lines 2). To the word lines 1 correspond common source lines (source diffusions 4), which, through source contacts 21, are connected to each other by source metal lines 5 arranged at regular intervals between matrix columns. The bit lines 2 connect, in their turn, respective drain regions 7 lines to each other, through drain contacts 22. Insulating oxide layers, not shown in FIG. 1, are interposed between the numerous source and drain regions and the related contacts. The presence of a defective memory cell (notable by means of the different representation 1xe2x80x3 in its word line) causes the flow of a leakage current IL.
Moreover, bump contacts (made of metal pad) 8 of boot-strap circuits, located in proper places of the device, which, through contacts 23, are connected to respective word lines 1, are shown. The bump contacts 8 are then connected to metal lines, not shown in FIG. 1, extending parallel to the word lines 1.
FIG. 2 schematically shows the section view taken along line IIxe2x80x94II of FIG. 1: on a P type substrate 6 there are N+type silicon regions, corresponding alternatively to source regions 4 and to drain regions 7, gate lines or word lines 1, insulating oxide layers 3, and a bit line 2 connected to the N+drain regions 7 through contacts 22.
In FIG. 3, showing schematically a section view taken along line IIIxe2x80x94III of FIG. 1, it can be noted the metal 5 connected to a N+type silicon layer corresponding to a source diffusion 4, disposed on the P type substrate 6, and a insulating oxide layer 3 on which some bit lines 2 are disposed. The metal 5 is connected to all the source diffusions through contacts 21.
FIG. 4 represents a section view taken along line IVxe2x80x94IV of FIG. 1, showing the metal 5 and the bit lines 2, these last connected through electrodes 22 to their respective N+type silicon regions 7 formed over the P type substrate 6, and spaced apart by means of insulating oxide regions 3.
FIG. 5 schematically shows a circuit diagram of the same matrix of FIG. 1, wherein the single memory (C) cells, constituted by N channel MOSFETs, with their related word lines 1 (WL0-WL5), bit lines 2 (BL0-BLn) and source diffusions 4 (SD0-SD2), these last connected to each other by means of metal 5, are more evident. The word lines 1 are addressed by a proper row decoder 13. The presence of the defective cell Cxe2x80x2 causes the leakage current IL flow in the bit line BL1 wherein said cell is, in the related source diffusion SD1 and in the metal line 5.
FIG. 6 shows the layout of a metal mask M1 of a portion of the matrix of FIG. 1, used in a manufacturing process step of the memory device, subsequent to that of forming the source 4 and drain 7 regions, the word lines 1 and bit lines 2, wherein the source metal lines 5 are formed, by means of proper openings 15, and the possible bump contacts 8 of the boot-strap circuits by means of proper openings 18.
With a memory cells matrix structured as above-mentioned, the localization of the leakage defect refers to the bit line in which the defective cell (placed in transistor Cxe2x80x2 of FIG. 5) is inserted, without a possible further localization inside the bit line itself, because of the connection of all the source electrodes of the memory cells: in a fault analysis process, in fact, by biasing the bit line wherein the possible defective cell is, e.g. at 1 V, it can be always noted a leakage current IL flow whatever it might be the voltage applied to the word lines.
To address the problem of localizing a possible leakage defect in one or more memory matrix cells, two preliminary concepts can be considered:
a leakage current variation can be obtained simply by biasing the source; particularly, if the bit line in which the leakage current flow occurs is biased to a determined drain voltage, usually 1 V, by biasing all the source diffusions to the same potential, the leakage current is canceled;
if it is possible to bias separately the single source diffusions, the cancellation of the leakage current occurs when the source diffusion of the cell producing leakage is biased to 1 V; by contrast, the bias of the other source diffusions does not produce any effect on the leakage current. In this way the indetermination of defect localization is reduced from all the cells constituting a determined bit line (some hundreds or thousands according to the device) to the two only cells of the bit line which have the common source diffusion biased in a proper manner.
At this point it could be thought of manufacturing a device ad hoc wherein the single source diffusions are decoded separately, like the word lines and the bit lines, but this would involve completely redesigning the device and the device would have a larger size. The mask set of such a device would be completely different compared to a conventional one, and the decision of using such a possibility should be taken as soon as the lot to be worked goes into production.
In view of the state of the art described, it is an object of the present invention to provide a method and apparatus for localizing point defects causing leakage currents in a non-volatile memory device that requires modifying only a minimum number of masks during the manufacturing process of the device itself.
According to the present invention, this and other objects are achieved by means of a method for localizing point defects causing column leakage currents in a non-volatile memory device, said device comprising a plurality of memory cells arranged in rows and columns in a matrix structure, source diffusions, and metal lines which connect said source diffusions to each other, comprising the steps of: modifying said memory device in order to make said source diffusions independent of each other and each one electrically connected to a respective row; sequentially biasing the single columns of said matrix; localizing the column to which at least one defective cell belongs, as soon as said leakage current flow occurs in the biased column; by keeping biased said localized column, biasing sequentially said single rows of said matrix to the same potential as that of said localized column; localizing a couple of said cells, wherein at least one of them involves said point defects, as soon as said leakage current flow does not occur.